Sub 50 - nm FinFET : PMOS ( revised 12 / 9 / 1999 )
نویسندگان
چکیده
High performance PMOSFETs with a gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. The 45 nm gate-length PMOS FinFET has an Idsat of 410 PA/Pm (or 820 PA/Pm depending on the definition of the width of a double-gate device) at Vd = Vg = 1.2 V and Tox = 2.5 nm. The quasi-planar nature of this variant of the double-gate MOSFETs makes device fabrication relatively easy using the conventional planar MOSFET process technologies. Simulation shows possible scaling to a 10–nm gate length.
منابع مشابه
Sub - 50 nm P - Channel FinFET
High-performance PMOSFETs with sub-50–nm gate-length are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short-channel effects. This vertical double-gate SOI MOSFET features: 1) a transistor channel which is formed on the vertical surfaces of an ultrathin Si fin and controlled by gate electrodes formed on both sides of the fin; 2) two gates which are self-...
متن کاملElectron Beam Lithography for the Fabrication of Future Device Demonstrators
Multi-gate transistors are considered to be the ultimate device concept for use in future CMOS generations. The so-called FinFET [1] is a variant with a straightforward process flow [2]. A three-dimensional sketch of the FinFET can be seen in Fig.1. The small channels benefit from superior electrostatic channel control, resulting in enhanced turn-off behavior. However, its fabrication demands e...
متن کاملA FinFET SRAM cell design with BTI robustness at high supply voltages and high yield at low supply voltages
In this paper, a SRAM cell structure which uses pMOS access transistors and predischarged bitlines is presented. By using the strained pMOS transistor technology, the degradation of the read static noise margin (SNM) at high supply voltages due to the aging, especially in the presence of symmetric stress, is suppressed. In contrast to conventional cell, the write margin of the proposed cell doe...
متن کاملDesign & Optimization of Finfet Based Schmitt Trigger Using Leakage Reduction Techniques
In this proposed work we are applying valuable power gating schemes to FinFET based Schmitt trigger to enhance its performance by reducing the leakage current in standby mode (off-state mode). The power gating schemes like Sleep Transistor approach and Multi-Threshold CMOS (MTCMOS) and Double-Threshold CMOS (DTCMOS) have been analysed and simulated which shows the tremendous reduction in the le...
متن کاملSwitched-Capacitor Dynamic Threshold PMOS (SC-DTPMOS) Transistor for High Speed Sub-threshold Applications
This work studies the effects of dynamic threshold design techniques on the speed and power of digital circuits. A new dynamic threshold transistor structure has been proposed to improve performances of digital circuits. The proposed switched-capacitor dynamic threshold PMOS (SC-DTPMOS) scheme employs a capacitor along with an NMOS switch in order to effectively reduce the threshold voltage of ...
متن کامل